R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 124

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Exception Handling
5.5.2
When an address error occurs, address error exception handling starts after the bus cycle causing
the address error ends and current instruction execution completes. The address error exception
handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the address error is generated, the
Even though an address error occurs during a transition to an address error exception handling, the
address error is not accepted. This prevents an address error from occurring due to stacking for
exception handling, thereby preventing infinitive stacking.
If the SP contents are not a multiple of 2 when an address error exception handling occurs, the
stacked values (PC, CCR, and EXR) are undefined.
When an address error occurs, the following is performed to halt the DTC and DMAC.
• The ERR bit of DTCCR in the DTC is set to 1.
• The ERRF bit of DMDR_0 in the DMAC is set to 1.
• The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate
Table 5.6 shows the state of CCR and EXR after execution of the address error exception
handling.
Table 5.6
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
Rev. 2.00 Sep. 16, 2009 Page 94 of 1036
REJ09B0414-0200
Interrupt Control Mode
0
2
start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
transfer.
Address Error Exception Handling
States of CCR and EXR after Address Error Exception Handling
I
1
1
CCR
UI



0
T
EXR
I2 to I0

7