R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 817
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 817 of 1070
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Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Bit Name
FLER
R
7
1
Initial
Value
1
0
0
0
R
6
0
R/W
R
R
R
R
R
5
0
Description
Reserved
These are read-only bits and cannot be modified.
Flash Memory Error
Indicates that an error has occurred during programming
or erasing the flash memory. When this bit is set to 1,
the flash memory enters the error protection state.
When this bit is set to 1, high voltage is applied to the
internal flash memory. To reduce the damage to the
flash memory, the reset must be released after the reset
input period (period of RES = 0) of at least 100 µs.
0: Flash memory operates normally (Error protection is
[Clearing condition]
•
1: An error occurs during programming/erasing flash
[Setting conditions]
•
•
•
•
invalid)
At a reset
memory (Error protection is valid)
When an interrupt, such as NMI, occurs during
programming/erasure.
When the flash memory is read during
programming/erasure (including a vector read and
an instruction fetch).
When the SLEEP instruction is executed during
programming/erasure (including software standby
mode).
When a bus master other than the CPU, such as the
DMAC and DTC, obtains bus mastership during
programming/erasure.
FLER
R
4
0
R
3
0
Rev. 2.00 Sep. 16, 2009 Page 787 of 1036
R
2
0
Section 22 Flash Memory
R
1
0
REJ09B0414-0200
(R)/W
SCO
0
0
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