R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 34

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Classification
DMA
External bus
extension
Rev. 2.00 Sep. 16, 2009 Page 4 of 1036
REJ09B0414-0200
Module/
Function
DMA
controller
(DMAC)
Data
transfer
controller
(DTC)
Bus
controller
(BSC)
Description
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Bus formats
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Two-channel DMA transfer available
Three activation methods (auto-request, on-chip module
interrupt, external request)
Three transfer modes (normal transfer, repeat transfer, block
transfer)
Dual or single address mode selectable
Extended repeat-area function
Allows DMA transfer over 55 channels (number of DTC
activation sources)
Activated by interrupt sources (chain transfer enabled)
Three transfer modes (normal transfer, repeat transfer, block
transfer)
Short-address mode or full-address mode selectable
16-Mbyte external address space
The external address space can be divided into eight areas,
each of which is independently controllable
 Chip-select signals (CS0 to CS7) can be output
 Access in two or three states can be selected for each area
 Program wait cycles can be inserted
 The period of CS assertion can be extended
 Idle cycles can be inserted
Bus arbitration function (arbitrates bus mastership among the
internal CPU, DMAC and DTC, and external bus masters)
External memory interfaces (for the connection of ROM, burst
ROM, SRAM, and byte control SRAM)
Address/data bus format: Support for both separate and
multiplexed buses (8-bit access or 16-bit access)
Endian conversion function for connecting devices in little-
endian format