R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 845

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7. Initialization is executed. The initialization program is downloaded together with the
8. The return value in the initialization program, the FPFR parameter is determined.
9. All interrupts and the use of a bus master other than the CPU are disabled during
10. FKEY must be set to H'5A and the user MAT must be prepared for programming.
programming program to the on-chip RAM. The entry point of the initialization program is at
the address which is 32 bytes after #DLTOP (start address of the download destination
specified by FTDAR). Call the subroutine to execute initialization by using the following
steps.
MOV.L #DLTOP+32,ER2
JSR
NOP
 The general registers other than ER0 and ER1 are held in the initialization program.
 R0L is a return value of the FPFR parameter.
 Since the stack area is used in the initialization program, a stack area of 128 bytes at the
 Interrupts can be accepted during execution of the initialization program. Make sure the
programming/erasure. The specified voltage is applied for the specified time when
programming or erasing. If interrupts occur or the bus mastership is moved to other than the
CPU during programming/erasure, causing a voltage exceeding the specifications to be
applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7
(I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting
bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2.
Accordingly, interrupts other than NMI are held and not executed. Configure the user system
so that NMI interrupts do not occur. The interrupts that are held must be executed after all
programming completes. When the bus mastership is moved to other than the CPU, such as to
the DMAC or DTC, the error protection state is entered. Therefore, make sure the DMAC does
not acquire the bus.
maximum must be allocated in RAM.
program storage area and stack area in the on-chip RAM and register values are not
overwritten.
@ER2
; Set entry address to ER2
; Call initialization routine
Rev. 2.00 Sep. 16, 2009 Page 815 of 1036
Section 22 Flash Memory
REJ09B0414-0200