R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 637
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.3.4
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
automatically transfers transmit data from TDR to TSR, and then sends the data to the TxD pin.
TSR cannot be directly accessed by the CPU.
16.3.5
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bits in SMR have different functions in normal mode and smart card interface mode.
• When SMIF in SCMR = 0
• When SMIF in SCMR = 1
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit
7
6
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Transmit Shift Register (TSR)
Serial Mode Register (SMR)
Bit Name
C/A
CHR
R/W
R/W
C/A
GM
7
0
7
0
Initial
Value
0
0
CHR
R/W
R/W
BLK
6
0
6
0
R/W
R/W
R/W
R/W
R/W
PE
PE
5
0
5
0
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
Character Length (valid only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is fixed
In clocked synchronous mode, a fixed data length of 8
bits is used.
and the MSB (bit 7) in TDR is not transmitted in
transmission.
R/W
R/W
O/E
O/E
4
0
4
0
Section 16 Serial Communication Interface (SCI)
STOP
BCP1
R/W
R/W
3
0
3
0
Rev. 2.00 Sep. 16, 2009 Page 607 of 1036
BCP0
R/W
R/W
MP
2
0
2
0
CKS1
CKS1
R/W
R/W
1
0
1
0
REJ09B0414-0200
CKS0
CKS0
R/W
R/W
0
0
0
0
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