R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 869
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(1)
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment
sequence is shown in figure 22.22.
(2)
After adjustment of the bit rate, the protocol for serial communications between the host and the
boot program is as shown below.
1. One-byte commands and one-byte responses
2. n-byte commands or n-byte responses
3. Error response
4. Programming of 128 bytes
These one-byte commands and one-byte responses consist of the inquiries and the ACK for
successful completion.
These commands and responses are comprised of n bytes of data. These are selections and
responses to inquiries.
The program data size is not included under this heading because it is determined in another
command.
The error response is a response to inquiries. It consists of an error response and an error code
and comes two bytes.
The size is not specified in commands. The size of n is indicated in response to the
programming unit inquiry.
Bit-Rate-Adjustment State
Communications Protocol
Host
Figure 22.22 Bit-Rate-Adjustment Sequence
H'00 (completion of adjustment)
H'E6 (boot response)
H'00 (30 times maximum)
(H'FF (error))
H'55
Rev. 2.00 Sep. 16, 2009 Page 839 of 1036
Measuring the
Boot program
1-bit length
Section 22 Flash Memory
REJ09B0414-0200
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