R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 567
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• NDRL
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3 to 0
Bit
7 to 4
3
2
1
0
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit Name
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Bit Name
NDR7
NDR6
NDR5
NDR4
Bit Name
NDR3
NDR2
NDR1
NDR0
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
0
0
0
All 1
Initial
Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
with PCR.
Description
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
with PCR.
Reserved
These bits are always read as 1 and cannot be modified.
Description
Reserved
These bits are always read as 1 and cannot be modified.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
with PCR.
Section 13 Programmable Pulse Generator (PPG)
Rev. 2.00 Sep. 16, 2009 Page 537 of 1036
REJ09B0414-0200
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