R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 99

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3.1
This LSI has six operating modes (modes 1, 2, 4, 5, 6, and 7). The operating mode is selected by
the setting of mode pins MD2 to MD0. Table 3.1 lists MCU operating mode settings.
Table 3.1
In this LSI, an advanced mode as the CPU operating mode and a 16-Mbyte address space are
available. The initial external bus widths are eight or 16 bits. As the LSI initiation mode, the
external extended mode, on-chip ROM initiation mode, or single-chip initiation mode can be
selected.
Modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory
can be programmed and erased. For details on the user boot mode and boot mode, see section 22,
Flash Memory.
Mode 7 is a single-chip initiation mode. All I/O ports can be used as general input/output ports.
The external address space cannot be accessed in the initial state, but setting the EXPE bit in the
system control register (SYSCR) to 1 enables to use the external address space. After the external
address space is enabled, ports H and I can be used as a data bus, and ports D, E, and F can be
used as an address output bus by specifying the data direction register (DDR) for each port.
MCU
Operating
Mode
1
2
4
5
6
7
Operating Mode Selection
0
0
1
1
1
1
MD2
MCU Operating Mode Settings
MD1
0
1
0
0
1
1
Section 3 MCU Operating Modes
MD0
1
0
0
1
0
1
CPU
Operating
Mode
Advanced
mode
Address
Space
16 Mbytes
LSI Initiation
Mode
User boot mode
Boot mode
On-chip ROM
disabled extended
mode
On-chip ROM
enabled extended
mode
Single-chip mode
Rev. 2.00 Sep. 16, 2009 Page 69 of 1036
Section 3 MCU Operating Modes
On-Chip
ROM
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
REJ09B0414-0200
Default Max.
16 bits
8 bits
8 bits
External Data
Bus Width
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits

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