R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 648

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 16, 2009 Page 618 of 1036
REJ09B0414-0200
Bit
5
4
Bit Name
ORER
FER
Initial
Value
0
0
R/W
R/(W)* Overrun Error
R/(W)* Framing Error
Description
Indicates that an overrun error has occurred during
reception and the reception ends abnormally.
[Setting condition]
•
[Clearing condition]
•
Indicates that a framing error has occurred during
reception in asynchronous mode and the reception
ends abnormally.
[Setting condition]
•
[Clearing condition]
•
When the next serial reception is completed while
RDRF = 1
In RDR, receive data prior to an overrun error
occurrence is retained, but data received after the
overrun error occurrence is lost. When the ORER
flag is set to 1, subsequent serial reception cannot
be performed. Note that, in clocked synchronous
mode, serial transmission also cannot continue.
When 0 is written to ORER after reading ORER = 1
Even when the RE bit in SCR is cleared, the ORER
flag is not affected and retains its previous value.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
whether it is 1 but the second stop bit is not
checked. Note that receive data when the framing
error occurs is transferred to RDR, however, the
RDRF flag is not set. In addition, when the FER flag
is being set to 1, the subsequent serial reception
cannot be performed. In clocked synchronous
mode, serial transmission also cannot continue.
When 0 is written to FER after reading FER = 1
Even when the RE bit in SCR is cleared, the FER
flag is not affected and retains its previous value.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)