R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 353

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.5.11
(1)
In single address mode, one byte, one word, or one longword of data is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU or DTC are executed in the bus released cycles.
In figure 9.34, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (read).
Single Address Mode (Read and Cycle Stealing)
Bus Cycles in Single Address Mode
Figure 9.34 Example of Transfer in Single Address Mode (Byte Read)
Address bus
RD
DACK
TEND
released
Bus
DMA read
cycle
released
Bus
DMA read
cycle
released
Bus
DMA read
cycle
Rev. 2.00 Sep. 16, 2009 Page 323 of 1036
released
Bus
Section 9 DMA Controller (DMAC)
Last transfer
DMA read
cycle
cycle
released
Bus
REJ09B0414-0200

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