R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 16

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
Section 9 DMA Controller (DMAC)................................................................. 259
9.1
9.2
9.3
Rev. 2.00 Sep. 16, 2009 Page xiv of xxviii
8.8.7
Address/Data Multiplexed I/O Interface........................................................................... 228
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
Idle Cycle.......................................................................................................................... 238
8.10.1
8.10.2
Bus Release....................................................................................................................... 248
8.11.1
8.11.2
8.11.3
Internal Bus....................................................................................................................... 251
8.12.1
Write Data Buffer Function .............................................................................................. 252
8.13.1
8.13.2
Bus Arbitration ................................................................................................................. 254
8.14.1
8.14.2
Bus Controller Operation in Reset.................................................................................... 257
Usage Notes ...................................................................................................................... 257
Features............................................................................................................................. 259
Input/Output Pins.............................................................................................................. 262
Register Descriptions........................................................................................................ 263
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
Extension of Chip Select (CS) Assertion Period............................................... 227
Address/Data Multiplexed I/O Space Setting ................................................... 228
Address/Data Multiplex.................................................................................... 228
Data Bus ........................................................................................................... 228
I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 229
Basic Timing..................................................................................................... 230
Address Cycle Control...................................................................................... 232
Wait Control ..................................................................................................... 233
Read Strobe (RD) Timing................................................................................. 233
Extension of Chip Select (CS) Assertion Period............................................... 235
DACK Signal Output Timing ........................................................................... 237
Operation .......................................................................................................... 238
Pin States in Idle Cycle..................................................................................... 247
Operation .......................................................................................................... 248
Pin States in External Bus Released State ........................................................ 249
Transition Timing ............................................................................................. 250
Access to Internal Address Space ..................................................................... 251
Write Data Buffer Function for External Data Bus .......................................... 252
Write Data Buffer Function for Peripheral Modules ........................................ 253
Operation .......................................................................................................... 254
Bus Transfer Timing......................................................................................... 255
DMA Source Address Register (DSAR) .......................................................... 264
DMA Destination Address Register (DDAR) .................................................. 265
DMA Offset Register (DOFR).......................................................................... 266
DMA Transfer Count Register (DTCR) ........................................................... 267
DMA Block Size Register (DBSR) .................................................................. 268
DMA Mode Control Register (DMDR)............................................................ 269