R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 669

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the
basic clock, data is latched at the middle of each bit, as shown in figure 16.3. Thus the reception
margin in asynchronous mode is determined by formula (1) below.
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 –
M = ( 0.5 –
M: Reception margin
N: Ratio of bit rate to clock (N = 16)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Figure 16.3 Receive Data Sampling Timing in Asynchronous Mode
2 × 16
2N
0
1
1
) – (L – 0.5) F –
8 clocks
Start bit
) × 100[%] = 46.875%
16 clocks
7
| D – 0.5 |
N
15 0
Section 16 Serial Communication Interface (SCI)
(1 + F )
Rev. 2.00 Sep. 16, 2009 Page 639 of 1036
D0
× 100
7
[%]
... Formula (1)
REJ09B0414-0200
15 0
D1

Related parts for R5F61662N50FPV