R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 24

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
17.1
17.2
17.3
17.4
17.5
17.6
17.7
Section 18 A/D Converter ................................................................................. 715
18.1
18.2
18.3
18.4
Rev. 2.00 Sep. 16, 2009 Page xxii of xxviii
Features............................................................................................................................. 681
Input/Output Pins.............................................................................................................. 683
Register Descriptions........................................................................................................ 684
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
17.3.7
17.3.8
17.3.9
Operation .......................................................................................................................... 697
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
17.4.6
17.4.7
Interrupt Request .............................................................................................................. 711
Bit Synchronous Circuit.................................................................................................... 712
Usage Notes ...................................................................................................................... 713
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Features............................................................................................................................. 715
Input/Output Pins.............................................................................................................. 717
Register Descriptions........................................................................................................ 717
18.3.1
18.3.2
18.3.3
Operation .......................................................................................................................... 723
2
C Bus Interface 2 (IIC2)................................................................ 681
Restriction on Bit Manipulation when Setting the MST and
TRS Bits in Multi-Master Mode ....................................................................... 714
I
I
I
I
I
Slave Address Register (SAR).......................................................................... 695
I
I
I
I
Master Transmit Operation............................................................................... 698
Master Receive Operation ................................................................................ 700
Slave Transmit Operation ................................................................................. 702
Slave Receive Operation................................................................................... 705
Noise Canceler.................................................................................................. 706
Example of Use................................................................................................. 707
Module Stop Function Setting .......................................................................... 713
Issuance of Stop Condition and Repeated Start Condition ............................... 713
WAIT Bit.......................................................................................................... 714
Restriction on Transfer Rate Setting Value in Multi-Master Mode.................. 714
Notes on Master Receive Mode........................................................................ 714
A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 718
A/D Control/Status Register (ADCSR) ............................................................ 719
A/D Control Register (ADCR) ......................................................................... 721
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ............................................................... 685
C Bus Control Register B (ICCRB) ............................................................... 686
C Bus Mode Register (ICMR)........................................................................ 688
C Bus Interrupt Enable Register (ICIER)....................................................... 690
C Bus Status Register (ICSR)......................................................................... 692
C Bus Transmit Data Register (ICDRT) ........................................................ 696
C Bus Receive Data Register (ICDRR).......................................................... 696
C Bus Shift Register (ICDRS)........................................................................ 696
C Bus Format.................................................................................................. 697