R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 738

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
Rev. 2.00 Sep. 16, 2009 Page 708 of 1036
REJ09B0414-0200
Note: 1.
2.
2
C Bus Interface 2 (IIC2)
No
No
No
Do not generate an interrupt during steps [1] to [3].
For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7].
In step [8], read ICDRR (dummy read).
Set ACKBT = 0 (ICIER)
Set ACKBT = 1 (ICIER)
Set RCVD = 1 (ICCRA)
Set RCVD = 0 (ICCRA)
Set MST = 0 (ICCRA)
Set TRS = 0 (ICCRA)
Master receive mode
Clear TEND in ICSR
Clear TDRE in ICSR
Dummy read ICDRR
Read RDRF in ICSR
Clear STOP in ICSR
Write BBSY = 0 and
Read STOP in ICSR
Dummy read ICSR
Read ICDRR
Read ICDRR
Read ICDRR
RDRF = 1?
receive -1?
RDRF = 1?
STOP = 1?
Figure 17.15 Sample Flowchart for Master Receive Mode
SCP = 0
Last
End
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag
[11] Issue the stop condition
[12] Wait for the creation of stop condition
[13] Read the receive data of the last byte
[14] Clear RCVD to 0
[15] Set to slave receive mode
Clear TEND, set to master receive mode, then clear TDRE*
Set acknowledge to the transmitting device*
Dummy read ICDRR*
Wait for 1 byte of data to be received*
Check if (last receive -1)*
Read the receive data*
Set acknowledge of the last byte. Disable continuous reception
(RCVD = 1).*
Read receive data of (last byte -1).*
Wait for the last byte to be received
2
1
*
2
2
2
2
2
1
*
2
1
*
2