R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 378

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Data Transfer Controller (DTC)
10.2.8
DTCCR specifies transfer information read skip.
Rev. 2.00 Sep. 16, 2009 Page 348 of 1036
REJ09B0414-0200
Bit
7 to 5
4
3
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to clear the flag.
Bit Name

RRS
RCHNE
DTC Control Register (DTCCR)
R/W

7
0
Initial
Value
All 0
0
0
R/W

6
0
R/W
R/W
R/W
R/W
R/W

5
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer
information read. A DTC vector number is always
compared with the vector number for the previous
activation. If the vector numbers match and this bit is
set to 1, the DTC data transfer is started without
reading a vector address and transfer information. If the
previous DTC activation is a chain transfer, the vector
address read and transfer information read are always
performed.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer
counter (CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the
chain transfer is enabled when CRAH is written to
CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer
numbers match.
RRS
R/W
4
0
RCHNE
R/W
3
0

R
2
0

R
1
0
R/(W)*
ERR
0
0