R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 743

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.7
17.7.1
Operation of the IIC2 can be disabled or enabled using the module stop control register. The initial
setting is for operation of the IIC2 to be halted. Register access is enabled by clearing the module
stop state. For details, see section 24, Power-Down Modes.
17.7.2
Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition. The
ninth falling edge can be confirmed by monitoring the SCLO bit in the I
(ICCRB).
If a stop or a repeated start condition is issued at certain timing in either of the following cases, the
stop or repeated start condition may be issued incorrectly.
• The rising time of the SCL signal exceeds the time given in section 17.6, Bit Synchronous
• The bit synchronous circuit is activated because a slave device holds the SCL bus low during
Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance).
the eighth clock.
Usage Notes
Module Stop Function Setting
Issuance of Stop Condition and Repeated Start Condition
Rev. 2.00 Sep. 16, 2009 Page 713 of 1036
Section 17 I
2
C bus control register B
2
C Bus Interface 2 (IIC2)
REJ09B0414-0200