R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 51

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Classification
16-bit timer
pulse unit (TPU)
Programmable
pulse generator
(PPG)
8-bit timer
(TMR)
Watchdog timer
(WDT)
Serial
communication
interface (SCI)
I
2 (IIC2)
2
C bus interface
Pin Name
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
PO15 to PO0
TMO0 to TMO7
TMCI0 to TMCI3
TMRI0 to TMRI3
WDTOVF
TxD0 to TxD4
RxD0 to RxD4
SCK0 to SCK4
SCL0, SCL1
SDA0, SDA1
I/O
Input/
output
Input/
output
Input/
output
Input/
output
Output
Output
Input
Input
Output
Output
Input
Input/
output
Input/
output
Input/
output
Description
Signals for TGRA_2 and TGRB_2. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_3 to TGRD_3. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_4 and TGRB_4. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Signals for TGRA_5 and TGRB_5. These pins are used as
input capture inputs, output compare outputs, or PWM
outputs.
Output pins for the pulse signals.
Output pins for the compare match signals.
Input pins for the external clock signals that drive for the
counters.
Input pins for the counter-reset signals.
Output pin for the counter-overflow signal in watchdog-timer
mode.
Output pins for data transmission.
Input pins for data reception.
Input/output pins for clock signals.
Input/output pins for clock signals for the IIC2. These pins
can drive the bus directly with NMOS open-drain output.
Input/output pins for data signals for the IIC2. These pins
can drive the bus directly with NMOS open-drain output.
Rev. 2.00 Sep. 16, 2009 Page 21 of 1036
Section 1 Overview
REJ09B0414-0200