R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 947

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 24 Power-Down Modes
24.8.7
Flowchart of Deep Software Standby Mode Operation
Figure 24.7 shows an example of flowchart of deep software standby mode operation. In this
example, reading the DPSRSTF bit determines whether a reset was generated by the RES pin or
exit from deep software standby mode, after the reset exception handling was performed.
When a reset was caused by the RES pin, deep software standby mode is entered after required
register settings.
When a reset was caused by exit from deep software standby mode, the IOKEEP bit is cleared
after the I/O ports setting. When the IOKEEP bit is cleared, the setting to avoid an undefined state
in Bφ output is also set.
In this flowchart, an interrupt source is checked by reading DPSIFR before the I/O ports setting. If
DPSIFR is read after the I/O ports setting, a source flag may be set without intention by the I/O
ports setting.
Rev. 2.00 Sep. 16, 2009 Page 917 of 1036
REJ09B0414-0200

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