R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 915

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
15
14
13
Bit Name
SSBY
OPE

Initial
Value
0
1
0
R/W
R/W
R/W
R/W
Description
Software Standby
Specifies the transition mode after executing the SLEEP
instruction
0: Shifts to sleep mode after the SLEEP instruction is
1: Shifts to software standby mode after the SLEEP
This bit does not change when clearing the software
standby mode by using interrupts and shifting to normal
operation. For clearing, write 0 to this bit. When the WDT
is used in watchdog timer mode, the setting of this bit is
disabled. In this case, a transition is always made to
sleep mode or all-module-clock-stop mode after the
SLEEP instruction is executed. When the SLPIE bit is set
to 1, this bit should be cleared to 0.
Output Port Enable
Specifies whether the output of the address bus and bus
control signals (CS0 to CS7, AS, RD, HWR, and LWR) is
retained or these lines are set to the high-Z state in
software standby mode or deep software standby mode.
0: In software standby mode or deep software standby
1: In software standby mode or deep software standby
Reserved
This bit is always read as 0. The write value should
always be 0.
executed
instruction is executed
mode, address bus and bus control signal lines are
high-impedance.
mode, output states of address bus and bus control
signals are retained.
Rev. 2.00 Sep. 16, 2009 Page 885 of 1036
Section 24 Power-Down Modes
REJ09B0414-0200