HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 114

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

When an NMI or another enabled interrupt is requested, the interrupt controller transfers the
interrupt request to the CPU and indicates the corresponding vector number. (When two or more
interrupts are requested, the interrupt controller selects the vector number of the interrupt with the
highest priority.) When notified of an interrupt request, at the end of the current instruction or
current hardware exception-handling sequence, the CPU starts the hardware exception-handling
sequence for the interrupt and latches the vector number.
Figure 4.5 shows the interrupt operation flow.
1. An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when
2. The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is
3. Among all accepted interrupt requests, the interrupt controller selects the request with the
4. When it receives the interrupt request, the CPU waits until completion of the current
5. In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the
6. Next the I bit in CCR is set to 1, masking all further interrupts except NMI.
7. The vector address corresponding to the vector number is generated, the vector table entry at
Figure 4.7 shows the interrupt timing sequence for the case in which the software interrupt-
handling routine is in on-chip ROM and the stack is in on-chip RAM.
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an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the
enable bit of that interrupt is set to 1.
cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests
remain pending.
highest priority and passes it to the CPU. Other interrupt requests remain pending.
instruction or hardware exception-handling sequence, then starts the hardware exception-
handling sequence for the interrupt and latches the interrupt vector number.
stack. See figure 4.6. The stacked PC indicates the address of the first instruction that will be
executed on return from the software interrupt-handling routine.
this vector address is loaded into the program counter, and execution branches to the software
interrupt-handling routine at the address indicated by that entry.