HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 345

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SDA
SCL
Internal clock
BBSY bit
Note that the clock may not be output properly during the next master send if receive data
(ICDR data) is read during the time between when the instruction to issue a stop condition is
executed (writing 0 to BBSY and SCP in ISSR) and when the stop condition is actually
generated.
In addition, overwriting of IIC control bits in order to change the send or receive operation
mode or to change settings, such as for example clearing the MST bit after completion of
master send or receive, should always be performed during the period indicated as (a) in Figure
13.21 below (after confirming that the BBSY bit in the ICCR register has been cleared to 0).
SCL
SDA
IRIC
Figure 13.21 Precautions when Reading Master Receive Data
Bit 0
Figure 13.20 IRIC Flag Clear Timing when WAIT = 1
8
Master receive mode
SCL determined to be low level
Execution of issue
stop condition instruction
(BBSY = 0 and SCP = 0 written)
A
9
SCL low level detected
VIH
SCL high level duration maintained
prohibited duration
ICDR read F
Stop condition generated
(BBSY = 0 read)
Stop condition
IRIC cleared
(a)
Start condition issued
Start condition
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