HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 274
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if
the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error
interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF,
FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is
1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is
transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and
receive-error interrupts are enabled.
Bit 3: MPIE
0
1
Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty
interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is
set to 1.
Bit 2: TEIE
0
1
Bit 1—Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud
rate generator. When the external clock source is selected, the SCK pin is automatically used for
input of the external clock signal.
Bit 1: CKE1
0
1
242
Description
The multiprocessor receive interrupt function is disabled.
(Normal receive operation)
The multiprocessor receive interrupt function is enabled. During the interval
before data with the multiprocessor bit set to 1 is received, the receive interrupt
request (RXI) and receive-error interrupt request (ERI) are disabled, the RDRF,
FER, PER, and ORER bits are not set in the serial status register (SSR), and
no data is transferred from the RSR to the RDR. The MPIE bit is cleared at the
following times:
1. When 0 is written in MPIE.
2. When data with the multiprocessor bit set to 1 is received.
Description
The TSR-empty interrupt request (TEI) is disabled.
The TSR-empty interrupt request (TEI) is enabled.
Description
Internal clock source
When C/A = 1, the serial clock signal is output at the SCK pin.
When C/A = 0, output depends on the CKE0 bit.
External clock source. The SCK pin is used for input.
(Initial value)
(Initial value)
(Initial value)
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