HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 132

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

External Clock Input: The external clock signal should have the same frequency as the desired
system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6.
Table 6.3
Item
Low pulse
width of external
clock input
High pulse
width of external
clock input
External clock
rise time
External clock
fall time
Clock pulse
width low
Clock pulse
width high
Table 6.4 shows the external clock output settling delay time. Figure 6.7 shows the timing for the
external clock output settling delay time. The oscillator and duty correction circuit have the
function of regulating the waveform of the external clock input to the EXTAL pin. When the
specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after
the elapse of the external clock output settling delay time (t
confirmed during the t
maintained during this time.
100
EXTAL
Clock Timing
Symbol
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
period, the reset signal should be driven low and the reset state
Figure 6.6 External Clock Input Timing
V
5.5 V
Min
40
40
—
—
0.3
0.4
0.3
0.4
CC
= 2.7 to
t
EXr
Max
—
—
10
10
0.7
0.6
0.7
0.6
t
EXH
V
5.5 V
Min
30
30
—
—
0.3
0.4
0.3
0.4
CC
= 4.0 to
Max
—
—
10
10
0.7
0.6
0.7
0.6
V
Min
20
20
—
—
0.3
0.4
0.3
0.4
DEXT
t
EXt
10%
CC
= 5.0 V
). As clock signal output is not
Max
—
—
5
5
0.7
0.6
0.7
0.6
t
EXL
Unit Test Conditions
ns
ns
ns
ns
t
t
t
t
cyc
cyc
cyc
cyc
Figure 6.6
ø
ø < 5 MHz 20-4
ø
ø < 5 MHz
V
5 MHz Figure
5 MHz
CC
0.5