HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 390

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.3
The D/A converter module has two built-in D/A converter circuits that can operate independently.
D/A conversion is performed continuously whenever enabled by the D/A control register. When a
new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The
converted result is output by setting the DAOE0 or DAOE1 bit to 1.
An example of conversion on channel 0 is given next. Figure 16.2 shows the timing.
1. Software writes the data to be converted in DADR0.
2. D/A conversion begins when the DAOE0 bit in DACR is set to 1. After a conversion delay,
3. If a new value is written in DADR0, conversion begins immediately. Output of the converted
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
358
ø
Address
DADR0
DAOE0
DA0
t
DCONV
analog output appears at the DA0 pin. The output value is AV
This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.
result begins after the conversion delay time.
: D/A conversion time
Operation
DADR0
write cycle
High-impedance state
DACR
write cycle
Figure 16.2 D/A Conversion (Example)
Conversion data (1)
t
DCONV
Conversion result (1)
DADR0
write cycle
CC
(DADR0 value)/256.
t
DCONV
Conversion data (2)
Conversion result (2)
DACR
write cycle