HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 376
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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15.4.2
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN
selected, after conversion of the first channel ends, conversion of the second channel (AN
AN
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN
described next. Figure 15.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
2. When A/D conversion of the first channel (AN
3. Conversion proceeds in the same way through the third channel (AN
4. When conversion of all selected channels (AN
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
344
AN
ADDRA. Next, conversion of the second channel (AN
and conversion of the first channel (AN
interrupt is requested at this time.
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN
5
) starts immediately. A/D conversion continues cyclically on the selected channels until the
0
to AN
Scan Mode (SCAN = 1)
2
are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
0
when CH2 = 0, AN
0
).
0
) starts again. If the ADIE bit is set to 1, an ADI
4
when CH2 = 1). When two or more channels are
0
0
) is completed, the result is transferred into
to AN
0
to AN
2
1
) is completed, the ADF flag is set to 1
) starts automatically.
2
) are selected in scan mode are
2
).
1
or
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