HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 199
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit 5—Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or falling
edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC
count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC becomes
simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a general-
purpose interrupt signal (which can be enabled or disabled by the ICICE bit).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5: ICFC
0
1
Bit 4—Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or falling
edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of the FRC
count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD becomes
simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a general-
purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4: ICFD
0
1
Bit 3—Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value
matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 3: OCFA
0
1
Description
To clear ICFC, the CPU must read ICFC after it has been set to 1, then write a
0 in this bit.
This bit is set to 1 when an FTIC input signal is received.
Description
To clear ICFD, the CPU must read ICFD after it has been set to 1, then write a
0 in this bit.
This bit is set to 1 when an FTID input signal is received.
Description
To clear OCFA, the CPU must read OCFA after it has been set to 1, then write
a 0 in this bit.
This bit is set to 1 when FRC = OCRA.
(Initial value)
(Initial value)
(Initial value)
167
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