HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 550
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HD64F3337YCP16
Manufacturer Part Number
HD64F3337YCP16
Description
IC H8 MCU FLASH 60K 84PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
Package
84PLCC
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
74
Interface Type
HIF/I2C/SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3337YCP16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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518
Increment address
NG
Write 32-byte data in RAM reprogram data
Store 32-byte program data in program
Transfer reprogram data to reprogram
H'FF dummy write to verify address
data area and reprogram data area
area consecutively to flash memory
Reprogram data computation
Figure 21.12 Program/Program-Verify Flowchart
Clear SWE bit in FLMCR1
Clear PSU bit in FLMCR2
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PSU bit in FLMCR2
Clear P bit in FLMCR1
Set PV bit in FLMCR1
Set P bit in FLMCR1
End of programming
Read verify data
data verification?
Program data =
End of 32-byte
Disable WDT
Enable WDT
Wait ( ) s
Wait ( ) s
Wait (x) s
Wait (y) s
Wait (z) s
Wait ( ) s
Wait ( ) s
Wait ( ) s
verify data?
OK
data area
m = 0?
m = 0
n = 1
Start
OK
OK
NG
NG
*5
*4
*1
*5
Start of programming
*5
End of programming
*5
*5
*5
*5
*2
*3
*4
*5
m = 1
Notes: *1 Data transfer is performed by byte transfer. The lower
Clear SWE bit in FLMCR1
Programming failure
Program
Data
*2 Verify data is read in 16-bit (word) units.
*3 If a bit for which programming has been completed in the 32-byte
*4 An area for storing program data (32 bytes) and reprogram data
*5 See section 23, Flash Memory Characteristics, for the values of
0
0
1
1
8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer
must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
programming loop fails the following verify phase, additional
programming is performed for that bit.
(32 bytes) must be provided in RAM. The contents of the latter
are rewritten as programming progresses.
x, y, z, , , , , , and N.
n
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
N?
0
1
0
1
Verify
Data
OK
*5
Reprogram
Data
1
0
1
1
NG
n
n + 1
Comments
Reprogramming is not
performed if program data
and verify data match
Programming incomplete;
reprogram
—
Still in erased state;
no action
Reprogram data storage
Program data storage
area (32 bytes)
area (32 bytes)
RAM
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