HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 15

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
5.7 Usage Notes
6.5 Floating-Point
Exceptions
• Enable/disable
exception handling
6.6.2 Pair Single-
Precision Data Transfer
6.7 Usage Notes
Page
182
194
196
197 to
207
Revision (See Manual for Details)
Description amended
2. If a general exception or interrupt occurs when SR.BL = 1
a. General exception
...
3. SPC when an exception occurs
a. Re-execution type general exception
b. Completion type general exception or interrupt
Description amended
For information on these possibilities, see the individual
instruction descriptions in chapter 9 of the SH-4 Software
Manual. The particulars differ demanding on the instruction. All
exception events that originate in the FPU are assigned as the
same exception event. The meaning of an exception is
determined by software by reading system register FPSCR and
interpreting the information it contains.
Description amended
In addition to the geometric operation instructions, the FPU
also supports high-speed data transfer instructions.
When FPSCR.SZ = 1, the FPU can perform data transfer by
means of pair single-precision data transfer instructions.
Newly added
When a general exception other than a user break occurs, a
manual reset is executed. The value in EXPEVT at this time
is H'0000 0020; the value of the SPC and SSR registers is
undefined.
The PC value for the instruction in which the general
exception occurred is set in SPC, and the instruction is re-
executed after returning from exception handling. If an
exception occurs in a delay slot instruction, however, the PC
value for the delay slot instruction is saved in SPC regardless
of whether or not the preceding delayed branch instruction
condition is satisfied.
The PC value for the instruction following that in which the
general exception occurred is set in SPC. If an exception
occurs in a branch instruction with delay slot, however, the
PC value for the branch destination is saved in SPC.
Rev.7.00 Oct. 10, 2008 Page xiii of lxxxiv
REJ09B0366-0700