HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 962

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 User Break Controller (UBC)
20.6
In the SH7750S, this function stops the clock supplied to the user break controller and is used to
minimize power dissipation when the chip is operating. Note that, if you use this function, you
cannot use the user break controller. This function is not provided in the SH7750.
20.6.1
Setting the MSTP5 bit of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the
user break controller to enter the stopped state. Follow steps (1) to (5) below to set the MSTP5 bit
to 1 and enter the stopped state.
(1) Initialize BBRA and BBRB to 0;
(2) Initialize BRCR to 0;
(3) Make a dummy read of BRCR;
(4) Read STBCR2, then set the MSTP5 bit in the read data to 1 and write back.
(5) Make two dummy reads of STBCR2.
Make sure that, if an exception or interrupt occurs while performing steps (1) to (5), you do not
change the values of these registers in the exception handling routine.
Do not read or write the following registers while the user break controller clock is stopped:
BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR. If these
registers are read or written, the value cannot be guaranteed.
20.6.2
The clock supply can be restarted by setting the MSTP5 bit of STBCR2 (inside the CPG) to 0. The
user break controller can then be operated again. Follow steps (6) and (7) below to clear the
MSTP5 bit to 0 to cancel the stopped state.
(6) Read STBCR2, then clear the MSTP5 bit in the read data to 0 and write the modified data
(7) Make two dummy reads of STBCR2.
As with the transition to the stopped state, if an exception or interrupt occurs while processing
steps (6) and (7), make sure that the values in these registers are not changed in the exception
handling routine.
Rev.7.00 Oct. 10, 2008 Page 876 of 1074
REJ09B0366-0700
back;
User Break Controller Stop Function
Transition to User Break Controller Stopped State
Cancelling the User Break Controller Stopped State