HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 532

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM
interface is used, timing for the negation of the strobe during read operations can be specified by
the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this
setting, see the description of the WCR3 register. When a byte control SRAM setting is made,
AnRDH should be cleared to 0.
Rev.7.00 Oct. 10, 2008 Page 446 of 1074
REJ09B0366-0700
Figure 13.13 SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2)
CKIO
A25−A0
CSn
RD/WR
RD
D63−D0
BS
Note: * When AnRDH is set to 1
TS1: Setup wait
WCR3.AnS
(0 to 1)
TS1
T1
Tw
Tw
Tw: Access wait
WCR2.AnW
(0 to 15)
Tw
Tw
T2
TH1, TH2: Hold wait
TH1
*
WCR3.AnH
(0 to 3)
TH2