HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 189

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.7.1
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the
entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field
bits [1:0].
In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0].
The following two kinds of operation can be used on the ITLB address array:
1. ITLB address array read
2. ITLB address array write
Address field
Legend:
VPN:
V:
E:
VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry
set in the address field.
VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to
the entry set in the address field.
Data field
Virtual page number
Validity bit
Entry
ITLB Address Array
31
31
1 1 1 1 0 0 1 0
Figure 3.13 Memory-Mapped ITLB Address Array
24
23
ASID:
:
VPN
Address space identifier
Reserved bits (0 write value, undefined
read value)
Section 3 Memory Management Unit (MMU)
Rev.7.00 Oct. 10, 2008 Page 103 of 1074
10 9 8 7
10 9
9 8 7
E
V
REJ09B0366-0700
ASID
0
0