HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 487

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.2.8
The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and
CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,
SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Initial value:
Initial value:
Initial value:
Initial value:
Memory Control Register (MCR)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
TRWL2 TRWL1 TRWL0
RASD
TCAS
R/W
R/W
R/W
R/W
SZ0
31
23
15
0
0
0
7
0
AMXEXT AMX2
MRSET
R/W
R/W
R/W
30
22
14
—
R
0
0
0
6
0
TRC2
TPC2
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
TRAS2
AMX1
TRC1
TPC1
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
Rev.7.00 Oct. 10, 2008 Page 401 of 1074
Section 13 Bus State Controller (BSC)
TRAS1
AMX0
TRC0
TPC0
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
TRAS0
RFSH
R/W
R/W
26
18
10
—
—
R
R
0
0
0
2
0
REJ09B0366-0700
RMODE
RCD1
R/W
R/W
R/W
BE
25
17
—
R
0
0
9
0
1
0
MODE
RCD0
EDO
R/W
SZ1
R/W
R/W
24
16
—
R
0
0
8
0
0
0