HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 555

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles
independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This
number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
BS
CKE
DACKn
(SA: IO ← memory)
Figure 13.28 Basic Timing for Synchronous DRAM Burst Read
Tr
Row
Row
Row
Trw
Tc1
H/L
c0
Tc2
Tc3
Tc4/Td1
Rev.7.00 Oct. 10, 2008 Page 469 of 1074
Section 13 Bus State Controller (BSC)
d0
Td2
d1
Td3
d2
Td4
REJ09B0366-0700
d3