HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 489

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written
with 0.
Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.
Bit 23: TCAS
0
1
Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected,
these bits specify the minimum number of cycles until RAS is asserted again after being negated.
When the synchronous DRAM interface is selected, these bits specify the minimum number of
cycles until the next bank active command after precharging.
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Bit 21: TPC2
0
1
Note:
Timing.
*
Inhibited in RAS down mode.
Bit 20: TPC1
0
1
0
1
CAS Negation Period
1
2
0
1
0
1
0
1
0
1
Bit 19: TPC0
Rev.7.00 Oct. 10, 2008 Page 403 of 1074
Section 13 Bus State Controller (BSC)
DRAM
0
1
2
3
4
5
6
7
RAS Precharge Interval
Synchronous DRAM
1* (Initial value)
2
3
4*
5*
6*
7*
8*
REJ09B0366-0700
(Initial value)