HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 956

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 User Break Controller (UBC)
2. Instruction access match on channel A, operand access match on channel B
3. Operand access match on channel A, instruction access match on channel B
4. Operand access matches on both channel A and channel B
20.3.9
1. Do not execute a post-execution instruction access break for the SLEEP instruction.
2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP
3. The value of the BL bit referenced in a user break exception depends on the break setting, as
Rev.7.00 Oct. 10, 2008 Page 870 of 1074
REJ09B0366-0700
Do not make a setting such that a single operand access will match the break conditions of
both channel A and channel B. There are no other restrictions. For example, sequential
operation is guaranteed even if two accesses within a single instruction match channel A and
channel B conditions in turn.
instruction.
follows.
a. Pre-execution instruction access break: The BL bit value before the executed instruction is
b. Post-execution instruction access break: The OR of the BL bit values before and after the
c. Operand access break (address/data): The BL bit value after the executed instruction is
d. In the case of an instruction that modifies the BL bit
Instruction B is 0 or 1 instruction after
instruction A
Instruction B is 2 or more instructions
after instruction A
Instruction B is 0 to 3 instructions after
instruction A
Instruction B is 4 or more instructions
after instruction A
referenced.
executed instruction is referenced.
referenced.
Usage Notes
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.