HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 878

IC SUPERH MPU ROMLESS 256BGA

HD6417750SBP200

Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SBP200

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
HITACHI
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Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 17 Smart Card Interface
Serial Data Transmission: As data transmission in smart card mode involves error signal
sampling and retransmission processing, the processing procedure is different from that for the
normal SCI. Figure 17.8 shows a sample transmission processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the FER/ERS error flag in SCSSR1 is cleared to 0.
3. Repeat steps 2 and 3 until it can be confirmed that the TEND flag in SCSSR1 is set to 1.
4. Write the transmit data to SCTDR1, clear the TDRE flag to 0, and perform the transmit
operation. The TEND flag is cleared to 0.
5. To continue transmitting data, go back to step 2.
6. To end transmission, clear the TE bit to 0.
With the above processing, interrupt handling is possible.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error
occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt
requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated. See
Interrupt Operation in section 17.3.6 below for details.
Rev.7.00 Oct. 10, 2008 Page 792 of 1074
REJ09B0366-0700

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