HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 949

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 7—Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included
in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset.
Bit 7: DBEB
0
1
Note: When the data bus is included in the break conditions, bits IDB1–0 in break bus cycle
Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break
is to be effected before or after the instruction is executed. This bit is not initialized by a power-on
reset or manual reset.
Bit 6: PCBB
0
1
Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B
are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset.
Bit 3: SEQ
0
1
Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see
section 20.4, User Break Debug Support Function) is to be used.
Bit 0: UBDE
0
1
register B (BBRB) should be set to 10 or 11.
Description
Data bus condition is not included in channel B conditions
Data bus condition is included in channel B conditions
Description
Channel B PC break is effected before instruction execution
Channel B PC break is effected after instruction execution
Description
Channel A and B comparisons are performed as independent conditions
Channel A and B comparisons are performed as sequential conditions
(channel A → channel B)
Description
User break debug function is not used
User break debug function is used
Rev.7.00 Oct. 10, 2008 Page 863 of 1074
Section 20 User Break Controller (UBC)
REJ09B0366-0700
(Initial value)