HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 539

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Wait State Control: As the clock frequency increases, it becomes impossible to complete all
states in one cycle as in basic access. Therefore, provision is made for state extension by using the
setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in
figure 13.18. Additional Tpc cycles (cycles used to secure the RAS precharge time) can be
inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from
RAS assertion to CAS assertion can be set to between 2 and 5 by inserting Trw cycles by means of
the RCD bit in MCR. Also, the number of cycles from CAS assertion to the end of the access can
be varied between 1 and 16 according to the setting of A2W2 to A2W0 or A3W2 to A3W0 in
WCR2.
CKIO
A25–A0
CSn
RD/WR
RAS
CAS
D63
(read)
D63
(write)
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
–
–
D0
D0
Tr1
Figure 13.18 DRAM Wait State Timing
Tr2
Row
Trw
Tc1
Rev.7.00 Oct. 10, 2008 Page 453 of 1074
Tcw
Column
Section 13 Bus State Controller (BSC)
Tc2
Tpc
REJ09B0366-0700
Tpc