HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 222
HD6417750SBP200
Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750SBP200
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 222 of 1164
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Section 4 Caches
4.6
To enable the management of the IC and OC by software, a program running in the privileged
mode is allowed to access their contents.
The contents of IC can be read and written by using MOV instructions in a P2-area program
running in the privileged mode. Operation is not guaranteed for access from a program in some
other area. Any branching to other areas must take place at least 8 instructions after this MOV
instruction.
The contents of IC can be read and written by using MOV instructions in a P1- or P2-area program
running in the privileged mode. Operation is not guaranteed if access is attempted from a program
running in some other area. A branch to the P0, U0, or P3 area must be made at least 8 instructions
after this MOV instruction.
The IC and OC are allocated to the P4 area of the physical memory space. The address and data
arrays of both the IC and OC are only accessible by their data fields. Longword operations must be
used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0
should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750S-
compatible mode, the configuration of the SH7750R's memory-mapped cache is the same as that
of the SH7750 or SH7750S.
Rev.7.00 Oct. 10, 2008 Page 136 of 1074
REJ09B0366-0700
Legend:
L: Longword specification bits
Address field
: Reserved bits (0 write value, undefined read value)
Data field
Memory-Mapped Cache Configuration (SH7750R)
31
31
1 1 1 1 0 1 0 1
Figure 4.11 Memory-Mapped OC Data Array
24
23
Longword data
14
13
Entry
5 4
L
2 1 0
0
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