HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 355

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.3.2
Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary,
SPC and SSR should be saved to the stack before executing the SLEEP instruction.
Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep
mode is exited and interrupt exception handling is executed. The code corresponding to the
interrupt source is set in the INTEVT register.
Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the RESET pin,
or a power-on or manual reset executed when the watchdog timer overflows.
9.4
9.4.1
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit
in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode.
After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to be
output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory that
requires refreshing, set the self-refresh function prior to making the transition to deep sleep mode.
In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at
the STATUS0 pin.
Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you
9.4.2
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip
peripheral module) or a reset.
Exit from Sleep Mode
Deep Sleep Mode
Transition to Deep Sleep Mode
Exit from Deep Sleep Mode
make a transition to deep sleep mode while DMA transfers are in progress, the results
of those transfers cannot be guaranteed.
Rev.7.00 Oct. 10, 2008 Page 269 of 1074
Section 9 Power-Down Modes
REJ09B0366-0700