HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 651

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
0
1
Note: BAVL (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
Bit 9: PR1
0
1
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4 (SH7750S)—Check Overrun for DREQ (COD): When this bit is set to 1, cancellation of
an accepted DREQ acceptance flag is enabled. When cancellation of an accepted DREQ
acceptance flag is enabled by setting COD to 1, clear CHCRn.DS to 0 and then negate DREQ (to
the high level). For details, see External Request Mode in section 14.3.2, DMA Transfer Requests.
Bit 4: COD
0
1
Note: When external request mode is used in the SH7750S, recommend setting COD to 1
Bit 4 (SH7750)—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
the BAVL pin function is enabled and this pin becomes an active-low output.
permanently.
Bit 8: PR0
0
1
0
1
Description
Normal DMA mode
On-demand data transfer mode
Description
DREQ acceptance flag cancellation disabled
DREQ acceptance flag cancellation enabled
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round robin mode
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 565 of 1074
REJ09B0366-0700
(Initial value)
(Initial value)
(Initial value)