HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 717

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5.4
1. Normal data transfer mode (channel 0)
2. Normal data transfer mode (channels 1 to 3)
3. Handshake protocol using the data bus (valid on channel 0 only)
CLK
DBREQ
BAVL
TR
A25–A0
D63–D0
RAS,
CAS, WE
TDACK
ID1, ID0
Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
Initial settings for channel 0 demand transfer must be DTR.ID = 00 and DTR.MD = 01, 10, or
11. In this case, only single address mode can be set for channel 0.
If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored.
a. The handshake protocol using the data bus can be executed only on channel 0. (Set
DTR.ID = 00, DTR.MD = 00, DTR.SZ ≠ 101 or 110. Operation is not guaranteed if
settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ = 101 or 110 are made.)
1st
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2
Notes on Use of DDT Module
2nd
Four requests can be queued
3rd
4th
5th
WT
CA
D0
D1
Section 14 Direct Memory Access Controller (DMAC)
D2
D3
Handshaking is necessary
to send additional requests
CA
WT
D0
Rev.7.00 Oct. 10, 2008 Page 631 of 1074
D1
D2
D3
CA
WT
D0
D1
Must be ignored
(no request transmitted)
D2
REJ09B0366-0700
D3
CA
WT