HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 808
HD6417750SBP200
Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750SBP200
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 808 of 1164
- Download datasheet (7Mb)
Section 15 Serial Communication Interface (SCI)
• When using the DMAC for transmission/reception, making a setting to disable RXI and TXI
When Using Synchronous External Clock Mode:
• Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
• Only set both TE and RE to 1 when external clock SCK is 1.
• In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles
When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero
1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF
will be set to 1 but copying to SCRDR1 will not be possible.
When Using DMAC: When using the DMAC for transmission/reception, make a setting to
suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is
made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by
the DMAC independently of the interrupt handling program.
SH7750 Only: When the following conditions are satisfied, the same data may be transmitted
multiple times.
• Conditions Under which Problem Occurs
• Workarounds
Rev.7.00 Oct. 10, 2008 Page 722 of 1074
REJ09B0366-0700
interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set,
interrupt requests to the interrupt controller will be cleared by the DMAC independently of the
interrupt handling program.
SCK has changed from 0 to 1.
after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to
SCRDR1 will not be possible.
a. External SCK clock input mode is selected (SCSCR1.CKE1 = 1).
b. Synchronous mode is selected (SCSMR1C/A = 1).
c. Transmit or receive is in progress (SCSCR1.TE = 1).
Conditions a. to c. must all be satisfied.
Workaround 1
⎯ PLL2 on
⎯ PLL2 off
As shown in figure 15.26, after synchronizing asynchronous input external clock SCK with
CKIO, input it to the SCK pin of the SH7750. In this case the SCK clock cycle minimum
value will be: peripheral clock cycle (Pck) × 8. Note that this workaround will reduce the
timing margins of the TxD and RxD pins synchronized with the SCK pin.
Operation cannot be guaranteed. (Usage prohibited.)
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