HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 821

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error
interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI)
request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1.
Bit 6: RIE
0
1
Note:
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF.
Bit 5: TE
0
1
Note:
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF.
Bit 4: RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER
Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be
made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set
to 1.
*
*
2. Serial transmission is started when a start bit is detected in this state.
Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be
An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then
clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can
be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or
by clearing the RIE and REIE bits to 0.
Serial transmission is started when transmit data is written to SCFTDR2 in this state.
flags, which retain their states.
made, the reception format decided, and the receive FIFO reset, before the RE bit is set
to 1.
Description
Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request disabled*
Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request enabled
Description
Transmission disabled
Transmission enabled*
Description
Reception disabled *
Reception enabled *
Section 16 Serial Communication Interface with FIFO (SCIF)
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Rev.7.00 Oct. 10, 2008 Page 735 of 1074
REJ09B0366-0700
(Initial value)
(Initial value)
(Initial value)