HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 423

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12.1
This LSI of microprocessors includes an on-chip 32-bit timer unit (TMU). The TMU of the
SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the
SH7750R has five channels (channels 0 to 4).
12.1.1
The TMU has the following features.
• Auto-reload type 32-bit down-counter provided for each channel
• Input capture function provided in channel 2
• Selection of rising edge or falling edge as external clock input edge when external clock is
• 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit
• For channels 0 to 2, selection of seven counter input clocks for each channel
• For channels 3 and 4, selection is made among five internal clocks (SH7750R only).
• Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock
• Two interrupt sources
• DMAC data transfer request capability
selected or input capture function is used
down-counter provided for each channel
External clock (TCLK), on-chip RTC output clock, five internal clocks (Pck/4, Pck/16, Pck/64,
Pck/256, Pck/1024) (Pck is the peripheral module clock)
is selected as the counter input clock; that is, timer operation continues even when the clock
has been stopped for the TMU.
Timer count operations using an external or internal clock are only possible when a clock is
supplied to the timer unit.
One underflow source (each channel) and one input capture source (channel 2)
On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is
generated.
Overview
Features
Section 12 Timer Unit (TMU)
Rev.7.00 Oct. 10, 2008 Page 337 of 1074
Section 12 Timer Unit (TMU)
REJ09B0366-0700