HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet
HD6413008VXI25
Specifications of HD6413008VXI25
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HD6413008VXI25 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3008 16 Hardware Manual Renesas 16-Bit Single-Chip ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.4.00 Aug. 20, 2007 Page iv of xliv REJ09B0395-0400 ...
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The H8/3008 is a high-performance single-chip microcomputer that incorporates the internal 32-bit H8/300H CPU and is also equipped with peripheral functions necessary for configuring a user system. The H8/3008 is built in with a variety of peripheral functions such as ...
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User manual for H8/3008 Document Title H8/3008 Hardware Manual H8/300H Series Software Manual User manual for development tools Document Title C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual H8S, H8/300 Series Simulator/Debugger User’s Manual High-performance Embedded Workshop User’s Manual H8S, ...
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Main Revisions for This Edition Item Page All — 1.1 Overview 1 1.2 Block Diagram 5 Figure 1.1 Block Diagram 1.3.1 Pin Arrangement 6 Table 1.2 Comparison of H8/3008 Pin Arrangements 8.2.10 Timer I/O 203 Control Register (TIOR) Bits 6 ...
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Item Page 9.4.1 8TCNT Count 261 Timing Figure 9.8 Count Timing for Internal Clock Input Figure 9.9 Count 262 Timing for External Clock Input (Both-Edge Detection) 9.4.2 Compare Match 263 Timing Figure 9.11 Timing of Clear by Compare Match Figure ...
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Item Page 9.4.3 Input Capture 264 Signal Timing Figure 9.13 Timing of Input Capture Input Signal 9.4.4 Timing of Status Flag Setting Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs Figure 9.15 CMFB 265 Flag Setting Timing when ...
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Item Page 9.4.5 Operation with 267 Cascaded Connection Compare Match Count Mode 9.7.1 Contention 272 between 8TCNT Write and Clear Figure 9.18 Contention between 8TCNT Write and Clear Rev.4.00 Aug. 20, 2007 page x of xliv REJ09B0395-0400 Revision (See Manual ...
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Item Page 9.7.2 Contention 273 between 8TCNT Write and Increment Figure 9.19 Contention between 8TCNT Write and Increment 9.7.3 Contention 274 between TCOR Write and Compare Match Figure 9.20 Contention between TCOR Write and Compare Match Revision (See Manual for ...
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Item Page 9.7.4 Contention 275 between TCOR Read and Input Capture Figure 9.21 Contention between TCOR Read and Input Capture 9.7.5 Contention 276 between Counter Clearing by Input Capture and Counter Increment Figure 9.22 Contention between Counter Clearing by Input ...
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Item Page 9.7.6 Contention 277 between TCOR Write and Input Capture Figure 9.23 Contention between TCOR Write and Input Capture 9.7.7 Contention 278 between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) Figure 9.24 Contention between 8TCNT ...
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Item Page 12.3.2 Operation in 356 Asynchronous Mode Figure 12.4 Sample Flowchart for SCI Initialization 13.3.5 Clock 396 Table 13.5 Bit Rates (bits/s) for Various BRR Settings (When Table 13.6 BRR 397 Settings for Typical Bit Rates ...
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Item Page 19.3 AC 481, 482 Table amended Characteristics Table 19.6 Bus Timing 19.4 A/D Conversion 486 Characteristics Table 19.8 A/D Conversion Characteristics C.7 Port B Block 616 Diagrams Figure C.7 (a) Port B Block Diagram (Pins PB and PB ...
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All trademarks and registered trademarks are the property of their respective owners. Rev.4.00 Aug. 20, 2007 page xvi of xliv REJ09B0395-0400 ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... 1.3.3 Pin Assignments in Each Mode ........................................................................... 12 Section 2 CPU ...................................................................................................................... 17 2.1 Overview........................................................................................................................... 17 2.1.1 Features................................................................................................................ 17 ...
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Power-Down State ............................................................................................... 51 2.9 Basic Operational Timing ................................................................................................. 51 2.9.1 Overview.............................................................................................................. 51 2.9.2 On-Chip Memory Access Timing........................................................................ 51 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 52 2.9.4 Access to External Address Space ....................................................................... 53 Section 3 MCU Operating ...
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Block Diagram ..................................................................................................... 76 5.1.3 Pin Configuration................................................................................................. 77 5.1.4 Register Configuration......................................................................................... 77 5.2 Register Descriptions ........................................................................................................ 78 5.2.1 System Control Register (SYSCR) ...................................................................... 78 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 79 5.2.3 IRQ Status Register ...
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Chip Select Signals .............................................................................................. 119 6.3.5 Address Output Method....................................................................................... 120 6.4 Basic Bus Interface ........................................................................................................... 122 6.4.1 Overview.............................................................................................................. 122 6.4.2 Data Size and Data Alignment............................................................................. 122 6.4.3 Valid Strobes........................................................................................................ 123 6.4.4 Memory Areas ..................................................................................................... 124 6.4.5 Basic Bus Control ...
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Register Descriptions ........................................................................................... 173 Section 8 16-Bit Timer 8.1 Overview........................................................................................................................... 177 8.1.1 Features................................................................................................................ 177 8.1.2 Block Diagrams ................................................................................................... 179 8.1.3 Pin Configuration................................................................................................. 182 8.1.4 Register Configuration......................................................................................... 183 8.2 Register Descriptions ........................................................................................................ 184 8.2.1 Timer Start Register (TSTR)................................................................................ 184 8.2.2 ...
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Pin Configuration................................................................................................. 246 9.1.4 Register Configuration......................................................................................... 247 9.2 Register Descriptions ........................................................................................................ 248 9.2.1 Timer Counters (8TCNT) .................................................................................... 248 9.2.2 Time Constant Registers A (TCORA) ................................................................. 249 9.2.3 Time Constant Registers B (TCORB) ................................................................. 250 9.2.4 Timer Control Register (8TCR)........................................................................... ...
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Register Descriptions ........................................................................................................ 287 10.2.1 Port A Data Direction Register (PADDR) ........................................................... 287 10.2.2 Port A Data Register (PADR) .............................................................................. 287 10.2.3 Port B Data Direction Register (PBDDR)............................................................ 288 10.2.4 Port B Data Register (PBDR) .............................................................................. 288 10.2.5 Next ...
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Section 12 Serial Communication Interface 12.1 Overview........................................................................................................................... 321 12.1.1 Features................................................................................................................ 321 12.1.2 Block Diagram..................................................................................................... 323 12.1.3 Pin Configuration................................................................................................. 324 12.1.4 Register Configuration......................................................................................... 325 12.2 Register Descriptions ........................................................................................................ 326 12.2.1 Receive Shift Register (RSR) .............................................................................. 326 12.2.2 Receive Data Register (RDR) ...
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Clock.................................................................................................................... 396 13.3.6 Transmitting and Receiving Data......................................................................... 398 13.4 Usage Notes ...................................................................................................................... 406 Section 14 A/D Converter 14.1 Overview........................................................................................................................... 411 14.1.1 Features................................................................................................................ 411 14.1.2 Block Diagram ..................................................................................................... 412 14.1.3 Pin Configuration................................................................................................. 413 14.1.4 Register Configuration......................................................................................... 414 14.2 Register Descriptions ...
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System Control Register (SYSCR) ................................................................................... 445 16.3 Operation .......................................................................................................................... 446 Section 17 Clock Pulse Generator 17.1 Overview........................................................................................................................... 447 17.1.1 Block Diagram..................................................................................................... 448 17.2 Oscillator Circuit............................................................................................................... 449 17.2.1 Connecting a Crystal Resonator........................................................................... 449 17.2.2 External Clock Input............................................................................................ 451 17.3 Duty ...
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Section 19 Electrical Characteristics 19.1 Absolute Maximum Ratings ............................................................................................. 471 19.2 DC Characteristics ............................................................................................................ 472 19.3 AC Characteristics ............................................................................................................ 479 19.4 A/D Conversion Characteristics........................................................................................ 485 19.5 D/A Conversion Characteristics........................................................................................ 487 19.6 Operational Timing ........................................................................................................... 488 19.6.1 Clock Timing ....................................................................................................... 488 ...
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Appendix G Package Dimensions Appendix H Comparison of H8/300H Series Product Specifications H.1 Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3006 and H8/3007, and H8/3008 ................................................................................ 632 H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ....... ...
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Section 1 Overview Figure 1.1 Block Diagram ................................................................................................... Figure 1.2 Pin Arrangement of H8/3008 (FP-100B or TFP-100B Package, Top View) ..... Section 2 CPU Figure 2.1 CPU Operating Modes ....................................................................................... 18 Figure 2.2 Memory Map...................................................................................................... 19 Figure 2.3 CPU Registers ...
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Figure 5.3 Timing of Setting of IRQnF ............................................................................... 88 Figure 5.4 Process Up to Interrupt Acceptance when ............................................. 93 Figure 5.5 Interrupt Masking State Transitions (Example) ................................................. 95 Figure 5.6 Process Up to Interrupt Acceptance when UE ...
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Section 7 I/O Ports Figure 7.1 Port 4 Pin Configuration..................................................................................... 144 Figure 7.2 Port 6 Pin Configuration..................................................................................... 148 Figure 7.3 Port 7 Pin Configuration..................................................................................... 151 Figure 7.4 Port 8 Pin Configuration..................................................................................... 153 Figure 7.5 Port 9 Pin Configuration..................................................................................... 156 Figure ...
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Figure 8.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ............. 224 Figure 8.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR................. 225 Figure 8.33 Timing of Setting of IMFA and IMFB by Compare Match ...
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Figure 9.23 Contention between TCOR Write and Input Capture......................................... 277 Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode................................................................................................................... 278 Section 10 Programmable Timing Pattern Controller (TPC) Figure 10.1 TPC Block Diagram ........................................................................................... 284 Figure 10.2 ...
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Figure 12.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A)................................................ 363 Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data........................ 364 Figure 12.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit ...
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Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN Figure 14.5 A/D Conversion Timing ..................................................................................... 426 Figure 14.6 External Trigger Input Timing ........................................................................... 427 Figure 14.7 Example of Analog Input Protection Circuit ...................................................... 429 Figure 14.8 Analog Input ...
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Figure 19.9 Basic Bus Cycle: Three-State Access with One Wait State ............................... 494 Figure 19.10 Bus-Release Mode Timing ................................................................................. 494 Figure 19.11 TPC and I/O Port Input/Output Timing.............................................................. 495 Figure 19.12 Timer Input/Output Timing................................................................................ 495 Figure 19.13 Timer External Clock ...
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Appendix G Package Dimensions Figure G.1 Package Dimensions (FP-100B)......................................................................... 630 Figure G.2 Package Dimensions (TFP-100B) ...................................................................... 631 Rev.4.00 Aug. 20, 2007, Page xxxvii of xliv REJ09B0395-0400 ...
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Section 1 Overview Table 1.1 Features .............................................................................................................. Table 1.2 Comparison of H8/3008 Pin Arrangements ....................................................... Table 1.3 Pin Functions...................................................................................................... Table 1.4 Pin Assignments in Each Mode (FP-100B, TFP-100B) ..................................... 12 Section 2 CPU Table 2.1 Instruction Classification.................................................................................... 27 Table 2.2 ...
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Section 6 Bus Controller Table 6.1 Bus Controller Pins ............................................................................................ 103 Table 6.2 Bus Controller Registers .................................................................................... 104 Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) .................................... 119 Table 6.4 Data Buses Used and Valid Strobes ................................................................... 124 ...
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Table 9.4 Operation of Channels 2 and 3 when Bit ICE is Set 8TCSR3 Register .. 257 Table 9.5 Types of 8-Bit Timer Interrupt Sources and Priority Order ............................... 269 Table 9.6 8-Bit Timer Interrupt Sources............................................................................. 270 ...
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Section 14 A/D Converter Table 14.1 A/D Converter Pins ............................................................................................ 413 Table 14.2 A/D Converter Registers .................................................................................... 414 Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD) ........... 415 Table 14.4 A/D Conversion Time (Single Mode) ................................................................ ...
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Appendix A Instruction Set Table A.1 Instruction Set..................................................................................................... 499 Table A.2 Operation Code Map (1)..................................................................................... 512 Table A.2 Operation Code Map (2)..................................................................................... 513 Table A.2 Operation Code Map (3)..................................................................................... 514 Table A.3 Number of States per Cycle................................................................................ 516 Table A.4 ...
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Overview The H8/3008 is a microcontroller (MCU) that integrates system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a ...
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Overview Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers eight 32-bit registers) High-speed ...
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Feature Description • 16-bit timer, Three 16-bit timer channels, capable of processing up to six pulse outputs or 3 channels six pulse inputs • 16-bit timer counter (channels • Two multiplexed output compare/input capture pins (channels 0 ...
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Overview Feature Description Operating modes Four MCU operating modes Mode Mode 1 Mode 2 Mode 3 Mode 4 • On-chip ROM is disabled in modes • Power-down Sleep mode state • Software standby mode • Hardware ...
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Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES RESO NMI φ/P6 7 LWR HWR RD AS BACK/P6 2 BREQ/P6 1 WAIT/ / ADTRG/CS /IRQ ...
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Overview 1.3 Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3008 is shown in figures 1.2 and 1.3. Differences in the H8/3008 pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, ...
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REF /AN /DA 84 ...
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Overview 1.3.2 Pin Functions Table 1.3 summarizes the pin functions. The 5 V operation models have a V connection of an external capacitor. Table 1.3 Pin Functions Pin No. FP-100B Type Symbol TFP-100B Power V 1*, 35 ...
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Pin No. FP-100B Type Symbol TFP-100B RES System 63 control RESO 10 STBY 62 BREQ 59 BACK 60 Interrupts NMI 64 IRQ to 17, 16, 5 IRQ Address 100 ...
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Overview Pin No. FP-100B Type Symbol TFP-100B 16-bit timer TCLKD TCLKA TIOCA to 99, 97 TIOCA 0 TIOCB to 100, 98, 96 Input/ 2 TIOCB 0 8-bit timer TMO , ...
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Pin No. FP-100B Type Symbol TFP-100B Analog power supply REF I/O ports 23 61 ...
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Overview 1.3.3 Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B, TFP-100B) Pin No. FP-100B TFP-100B Mode ...
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Pin No. FP-100B TFP-100B Mode ...
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Overview Pin No. FP-100B TFP-100B Mode /BREQ /BACK 2 φ 61 STBY 62 RES 63 64 NMI EXTAL 67 XTAL HWR 71 ...
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Pin No. FP-100B TFP-100B Mode /IRQ /CS /ADTRG / /TP /TCLKA /TP /TCLKB /TP /TIOCA 2 ...
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Overview Rev.4.00 Aug. 20, 2007 Page 16 of 638 REJ09B0395-0400 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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CPU ⎯ 32 ÷ 16-bit register-register divide: • Two CPU operating modes ⎯ Normal mode ⎯ Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, ...
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Address Space Figure 2.2 shows a simple memory map for the H8/3008. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further ...
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CPU 2.4 Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, ...
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CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. ...
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Bit 2—Zero Flag (Z): Set indicate zero data, and cleared indicate non-zero data. Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared other times. Bit 0—Carry ...
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CPU 2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte ...
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General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend: ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit Figure ...
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CPU Data Type 1-bit data Byte data Word data Longword data When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev.4.00 Aug. 20, 2007 Page ...
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Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 64 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction Data transfer MOV, PUSH* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, ...
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CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction #xx Rn Data MOV BWL BWL transfer ⎯ ⎯ POP, PUSH ⎯ ⎯ MOVFPE, MOVTPE ...
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Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General ...
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CPU Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) ...
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Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers immediate data and data in a general register. ...
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CPU Instruction Size* Function Rd ÷ Rs → Rd DIVXU B/W Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → ...
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Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → ...
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CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or ...
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Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C BOR B ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified ...
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CPU Table 2.8 Branching Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE ...
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Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling ⎯ RTE Returns from an exception-handling routine ⎯ SLEEP Causes a transition to the power-down state (EAs) → CCR LDC B/W Moves the source operand contents ...
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CPU Table 2.10 Block Transfer Instruction Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B repeat until else next; EEPMOV.W ⎯ ≠ 0 then repeat until else next; Block transfer instruction. This instruction transfers the number ...
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Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, ...
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CPU Before Execution of BCLR Instruction Input/output Input Input DDR 0 0 Execution of BCLR Instruction BCLR #0, @P4DDR ; Execute BCLR instruction on DDR After Execution of BCLR Instruction Input/output ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct ...
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CPU Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents to ...
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CPU Table 2.13 Effective Address Calculation Rev.4.00 Aug. 20, 2007 Page 44 of 638 REJ09B0395-0400 ...
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Rev.4.00 Aug. 20, 2007 Page 45 of 638 REJ09B0395-0400 2. CPU ...
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Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 ...
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CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector ...
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End of bus release Bus-released state End of exception handling Exception-handling state RES = "High" 1 Reset state* Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. From any ...
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CPU the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2.14 shows the stack after the exception-handling sequence. SP−4 SP−3 SP−2 SP−1 Stack area SP (ER7) Before exception handling starts ...
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The reset state can also be entered by a watchdog timer overflow. For details see section 11, Watchdog Timer. 2.8.7 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software ...
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CPU φ Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Figure 2.15 On-Chip Memory Access Cycle φ Address bus AS RD HWR LWR , , , D to ...
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Address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Figure 2.17 Access Cycle for On-Chip Supporting Modules φ Address bus AS RD HWR LWR , , , ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3008 has four operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input at these ...
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MCU Operating Modes Modes are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space of 1 Mbyte. ...
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MDS0 are read-only bits. The mode pin (MD MDCR is read. 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3008. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W Software standby Enables ...
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MCU Operating Modes Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 18, Power-Down State.) When software standby mode is exited by an external interrupt, and a transition is ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as an interrupt ...
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MCU Operating Modes 3.4 Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If ...
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Pin Functions in Each Operating Mode The pin functions of ports and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode ...
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MCU Operating Modes 3.6 Memory Map in Each Operating Mode Figure 3.1 shows memory map of the H8/3008. In the expanded modes, the address space is divided into eight areas. The initial bus mode differs between modes 1 and ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 Area 2 H'5FFFF H'60000 External Area 3 H'7FFFF address space H'80000 Area 4 H'9FFFF H'A0000 Area ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or ...
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Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset Exception • Interrupts ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Exception Handling 4.2 Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) 4. Exception Handling Rev.4.00 Aug. 20, 2007 Page 69 of 638 REJ09B0395-0400 ...
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Exception Handling φ RES Address bus RD HWR LWR , High (1), (3) Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling ...
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Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 27 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting ...
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Exception Handling 4.5 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP−4 SP−3 SP−2 SP−1 SP (ER7) → Stack area Before exception handling SP−4 SP−3 SP−2 ...
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Notes on Stack Usage When accessing word data or longword data, the H8/3008 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer ...
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Exception Handling SP TRAPA instruction executed SP set to H'FFFEFF Legend: CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: The diagram illustrates modes 3 and 4. Figure 4.6 Operation when SP Value ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in ...
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Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . TEI TEIE Interrupt controller Legend: ISCR: IRQ ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Interrupt Controller Registers 1 ...
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Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level of ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
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Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 0 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 1 16-bit ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W Priority level B7 Selects the priority level of 8-bit timer channel 0, ...
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Interrupt Controller Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 0 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) 1 ...
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Bit 7 ⎯ Initial value 0 ⎯ Read/Write Reserved bits Note: Only 0 can be written, to clear flags. * ISR is initialized to H' reset and in hardware standby mode. Bits 7 and 6—Reserved: These bits can ...
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Interrupt Controller Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0—IRQ to IRQ Enable (IRQ5E to IRQ0E): These bits enable or disable 5 0 IRQ ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ IRQ can be used to exit software standby mode. 0 NMI: NMI is the highest-priority interrupt and is ...
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Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 ⎯ Reserved WOVI Watchdog (interval timer) timer ⎯ Reserved ADI (A/D end) A/D IMIA0 ...
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Interrupt Controller Interrupt Source Origin IMIA2 16-bit timer (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) ⎯ Reserved CMIA0 8-bit timer (compare match channel A0) 0/1 CMIB0 (compare match B0) CMIA1/CMIB1 ...
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Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 RXI1 (receive data full 1) TXI1 (transmit data empty ...
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Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3008 handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes TEI1 Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when ...
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Interrupt Controller • interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it ...
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All interrupts are unmasked ← Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when • interrupt condition occurs and the corresponding interrupt enable ...
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Interrupt Controller Priority level 1? No IRQ 0 Yes IRQ Figure 5.6 Process Up to Interrupt Acceptance when Rev.4.00 Aug. 20, 2007 Page 96 of 638 REJ09B0395-0400 Program execution state Interrupt requested? Yes ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception ...
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Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item 1 ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one ...
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Section 6 Bus Controller 6.1 Overview The H8/3008 has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently ...
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Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. Area Internal address bus decoder WAIT Internal signals CPU bus request signal CPU bus acknowledge signal Legend: ABWCR: Bus width control register ASTCR: Access ...
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Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write ...
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Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers 1 Address* Name H'EE020 Bus width control register H'EE021 Access state control register H'EE022 Wait control register H H'EE023 Wait control register ...
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Bits 7 to 0—Area Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits ABW7 to ABW0 Description 0 Areas are 16-bit ...
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Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number ...
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
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Bus Controller WCRL 7 6 Bit W31 W30 Initial value 1 1 Read/Write R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Bus Controller 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 A23E Initial value 1 ...
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Bit 5—Address 21 Enable (A21E): Enables this bit enables A output from PA 21 and PA has its ordinary port functions. 6 Bit 5 A21E Description the input/output ...
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Bus Controller BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the area division unit, selects the extended memory map, and enables or disables WAIT pin input. BCR is initialized to H' ...
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Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit is valid in modes 3 and 4, and is invalid in modes 1 and 2. Bit 1 RDEA Description 0 Area divisions are as follows: ...
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Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals output of a chip select signal CS corresponding pin ...
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Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. Bit 7 6 ⎯ ⎯ Initial value 1 1 ⎯ ⎯ Read/Write ...
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Bus Controller 6.3 Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1- Mbyte modes Mbytes in the 16-Mbyte modes. Figure ...
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H'000000 Area 0 2 Mbytes H'1FFFFF H'200000 Area 1 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes H'5FFFFF H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5 2 Mbytes H'BFFFFF H'C00000 Area 6 2 ...
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Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal ...
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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL ABWn ASTn Wn1 ⎯ ⎯ Note 6.3.3 Memory Interfaces As its memory ...
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Bus Controller Output Output register (CSCR). A reset leaves pins the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports. ...
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Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H Series. Addresses are always updated between bus cycles. Address Update Mode 2: In address update mode 2, address updating is performed only in external space accesses. ...
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Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size ...
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In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd ...
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Bus Controller Table 6.4 Data Buses Used and Valid Strobes Access Read/ Area Size Write 8-bit access Byte Read area Write 16-bit access Byte Read area Write Word Read Write Notes: 1. Undetermined data means that unpredictable data is ...
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Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D pin is always high. Wait states can be inserted. φ Address bus ...
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Bus Controller 8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper data bus (D pin is always high. Wait states cannot be inserted. Address bus Read access Write access ...
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Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D accesses to even addresses and the lower data bus (D states can be ...
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Bus Controller φ Address bus Read access HWR LWR Write access Note Figure 6.12 ...
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Address bus Read access HWR LWR Write access Note Figure ...
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Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D even addresses and the lower data bus (D be inserted. ...
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Address bus Read access HWR LWR Write access Note Figure 6.15 Bus Control Signal ...
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Bus Controller Address bus Read access Write access Note Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) 6.4.6 Wait Control When accessing external space, the H8/3008 can extend the bus cycle ...
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Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low ...
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Bus Controller 6.5 Idle Cycle 6.5.1 Operation When the H8/3008 chip accesses external space, it can insert a 1-state idle cycle (T cycles in the following cases: when read accesses between different areas occur consecutively, and when a write ...
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In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. ...
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Bus Controller Bus cycle A Bus cycle φ Address bus RD CSn Simultaneous change of RD and CSn: possibility of mutual overlap (a) Idle cycle not inserted Figure 6.20 Example of Idle Cycle Operation ...
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Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. The bus master can be either the CPU or an external bus master. When a bus master has the bus right it can ...
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Bus Controller External Bus Master: When the BRLE bit is set BRCR, the bus can be released to an external bus master. The external bus master has highest priority, and requests the bus right from the ...
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When making a transition to software standby mode, if there is contention with a bus request from an external bus master, the BACK and strobe states may be indefinite when the transition is made. When using software standby mode, clear ...
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Bus Controller φ Address bus BREQ Pin Input Timing 6.7.2 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to ...
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Overview The H8/3008 has six input/output ports (ports and B) and one input-only port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7.1. ...
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I/O Ports Port Description Pins • Port 8 P8 /CS 5-bit I/O port 4 • have 2 0 schmitt inputs P8 /IRQ 3 ADTRG P8 /IRQ 2 P8 /IRQ 1 P8 /IRQ 0 Port 9 • ...
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Port Description Pins Port B • PB /TP 8-bit I/O port /TP 0 Legend: SCI0: Serial communication interface channel 0 ...
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I/O Ports 7.2 Port 4 7.2.1 Overview Port 8-bit input/output port which also functions as a data bus. It's pin configuration is shown in figure 7.1. The pin functions differ depending on the operating mode. In ...
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Register Descriptions Table 7.2 summarizes the registers of port 4. Table 7.2 Port 4 Registers Address* Name H'EE003 Port 4 data direction register H'FFFD3 Port 4 data register H'EE03E Port 4 input pull-up MOS control register Note: * Lower ...
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I/O Ports Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4. When port 4 functions as an output port, the value of this register is output. When a bit in ...
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Table 7.3 summarizes the states of the input pull-up MOS in each operating mode. Table 7.3 Input Pull-Up MOS Transistor States (Port 4) Mode Reset 8-bit bus mode Off 16-bit bus mode Legend: Off: The input pull-up ...
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I/O Ports 7.3 Port 6 7.3.1 Overview Port 8-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output. The ...
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Bit 7 is reserved fixed at 1, and cannot be modified. Bit 7 ⎯ P6 DDR Initial value 1 ⎯ Read/Write Reserved bit • Modes (Expanded Modes) P6 functions as the clock output pin (φ) ...
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I/O Ports Table 7.5 Port 6 Pin Functions in Modes Pin Pin Functions and Selection Method P6 /φ Bit PSTOP in MSTCRH selects the pin function. 7 PSTOP Pin function LWR Functions as LWR regardless of ...
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Port 7 7.4.1 Overview Port 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. ...
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I/O Ports Port 7 Data Register (P7DR) Bit ⎯ Initial value * Read/Write R Note: * Determined by pins When port 7 is read, the pin logic levels are always read. P7DR ...
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Port 8 pins Port IRQ 7.5.2 Register Descriptions Table 7.7 summarizes the registers of port 8. ...
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I/O Ports In the H8/3008, following a reset P8 P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H' reset and in hardware standby mode. In ...