HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 313

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Compare Match Count Mode
• Channels 0 and 1:
• Channels 2 and 3:
⎯ Setting when Input Capture Occurs
⎯ Counter Clear Specification
⎯ OVF Flag Operation
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
Channels 0 and 1 are controlled independently.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
Channels 2 and 3 are controlled independently.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR3, the compare match register function of TCORB2 in
• TMIO
• The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3
• TMIO
• If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
• The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits
• The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
• The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
accordance with the lower 8-bit compare match conditions.
and input capture occurs.
in 8TCSR2.
8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.
cannot be cleared independently.
overflows (from H'FFFF to H'0000).
H'FF to H'00).
channel 0 cannot be used.
channel 2 cannot be used.
3
3
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR3 is in
pin input capture input signal edge detection is selected by bits OIS3 and OIS2
Rev.4.00 Aug. 20, 2007 Page 267 of 638
REJ09B0395-0400
9. 8-Bit Timers