HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 34

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 8.31
Figure 8.32
Figure 8.33
Figure 8.34
Figure 8.35
Figure 8.36
Figure 8.37
Figure 8.38
Figure 8.39
Figure 8.40
Figure 8.41
Figure 8.42
Figure 8.43
Figure 8.44
Section 9 8-Bit Timers
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Figure 9.12
Figure 9.13
Figure 9.14
Figure 9.15
Figure 9.16
Figure 9.17
Figure 9.18
Figure 9.19
Figure 9.20
Figure 9.21
Figure 9.22
Rev.4.00 Aug. 20, 2007 Page xxxii of xliv
REJ09B0395-0400
Contention between Counter Clearing by Input Capture and Counter
Increment............................................................................................................ 236
CMF Flag Setting Timing when Compare Match Occurs.................................. 264
Contention between Counter Clearing by Input Capture and Counter
Increment............................................................................................................ 276
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ............. 224
Timing for Setting 16-Bit Timer Output Level by Writing to TOLR................. 225
Timing of Setting of IMFA and IMFB by Compare Match ............................... 226
Timing of Setting of IMFA and IMFB by Input Capture................................... 227
Timing of Setting of OVF .................................................................................. 228
Timing of Clearing of Status Flags .................................................................... 228
Contention between 16TCNT Write and Clear .................................................. 230
Contention between 16TCNT Word Write and Increment................................. 231
Contention between 16TCNT Byte Write and Increment .................................. 232
Contention between General Register Write and Compare Match..................... 233
Contention between 16TCNT Write and Overflow............................................ 234
Contention between General Register Read and Input Capture ......................... 235
Contention between General Register Write and Input Capture ........................ 237
Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0) ......................... 245
8TCNT Access Operation (CPU Writes to 8TCNT, Word) ............................... 259
8TCNT Access Operation (CPU Reads 8TCNT, Word).................................... 259
8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte).................. 259
8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) ................. 260
8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)....................... 260
8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte) ...................... 260
Count Timing for Internal Clock Input............................................................... 261
Count Timing for External Clock Input (Both-Edge Detection) ........................ 262
Timing of Timer Output ..................................................................................... 262
Timing of Clear by Compare Match................................................................... 263
Timing of Clear by Input Capture ...................................................................... 263
Timing of Input Capture Input Signal ................................................................ 264
CMFB Flag Setting Timing when Input Capture Occurs ................................... 265
Timing of OVF Setting....................................................................................... 265
Example of Pulse Output.................................................................................... 271
Contention between 8TCNT Write and Clear .................................................... 272
Contention between 8TCNT Write and Increment............................................. 273
Contention between TCOR Write and Compare Match..................................... 274
Contention between TCOR Read and Input Capture.......................................... 275