HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 55

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Type
System
control
Interrupts
Address
bus
Data bus
Bus control
Symbol
RES
RESO
STBY
BREQ
BACK
NMI
IRQ
IRQ
A
D
CS
CS
AS
RD
HWR
LWR
WAIT
23
15
7
0
to A
to D
5
0
to
to
0
0
Pin No.
FP-100B
TFP-100B
63
10
62
59
60
64
17, 16,
90 to 87
97 to 100,
56 to 45,
43 to 36
34 to 23,
21 to 18
2 to 5,
88 to 91
69
70
71
72
58
I/O
Input
Output
Input
Input
Output
Input
Input
Output
Input/
output
Output
Output
Output
Output
Output
Input
Name and Function
Reset input: When driven low, this pin resets the
chip. This pin must be driven low at power-up.
Reset output: Outputs the reset signal generated
by the watchdog timer to external devices
Standby: When driven low, this pin forces
a transition to hardware standby mode
Bus request: Used by an external bus master to
request the bus right
Bus request acknowledge: Indicates that the
bus has been granted to an external bus master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable interrupt
request pins
Address bus: Outputs address signals
Data bus: Bidirectional data bus
Chip select: Select signals for areas 7 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from the
external address space
High write: Goes low to indicate writing to the
external address space; indicates valid data on
the upper data bus (D
Low write: Goes low to indicate writing to the
external address space; indicates valid data on
the lower data bus (D
Wait: Requests insertion of wait states in bus
cycles during access to the external address
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Rev.4.00 Aug. 20, 2007 Page 9 of 638
7
15
to D
to D
0
).
8
).
REJ09B0395-0400
1. Overview