HD6413008VXI25 Renesas Electronics America, HD6413008VXI25 Datasheet - Page 38

• Manufacturer Part Number: HD6413008VXI25
• Description: MCU 3V 0K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD6413008VXI25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 19.9
Figure 19.10
Figure 19.11
Figure 19.12
Figure 19.13
Figure 19.14
Figure 19.15
Appendix C I/O Port Block Diagrams
Figure C.1
Figure C.2 (a) Port 6 Block Diagram (Pin P6
Figure C.2 (b) Port 6 Block Diagram (Pin P6
Figure C.2 (c) Port 6 Block Diagram (Pin P6
Figure C.2 (d) Port 6 Block Diagram (Pin P6
Figure C.3 (a) Port 7 Block Diagram (Pins P7
Figure C.3 (b) Port 7 Block Diagram (Pins P7
Figure C.4 (a) Port 8 Block Diagram (Pin P8
Figure C.4 (b) Port 8 Block Diagram (Pins P8
Figure C.4 (c) Port 8 Block Diagram (Pin P8
Figure C.4 (d) Port 8 Block Diagram (Pin P8
Figure C.5 (a) Port 9 Block Diagram (Pin P9
Figure C.5 (b) Port 9 Block Diagram (Pin P9
Figure C.5 (c) Port 9 Block Diagram (Pin P9
Figure C.5 (d) Port 9 Block Diagram (Pin P9
Figure C.5 (e) Port 9 Block Diagram (Pin P9
Figure C.5 (f) Port 9 Block Diagram (Pin P9
Figure C.6 (a) Port A Block Diagram (Pins PA
Figure C.6 (b) Port A Block Diagram (Pins PA
Figure C.6 (c) Port A Block Diagram (Pins PA
Figure C.7 (a) Port B Block Diagram (Pins PB
Figure C.7 (b) Port B Block Diagram (Pins PB
Figure C.7 (c) Port B Block Diagram (Pin PB
Figure C.7 (d) Port B Block Diagram (Pin PB
Figure C.7 (e) Port B Block Diagram (Pin PB
Figure C.7 (f) Port B Block Diagram (Pin PB
Appendix D Pin States
Figure D.1
Figure D.2
Rev.4.00 Aug. 20, 2007 Page xxxvi of xliv
REJ09B0395-0400
Basic Bus Cycle: Three-State Access with One Wait State ............................... 494
Bus-Release Mode Timing ................................................................................. 494
SCI Input/Output Timing in Synchronous Mode ............................................... 496
TPC and I/O Port Input/Output Timing.............................................................. 495
Timer Input/Output Timing................................................................................ 495
Timer External Clock Input Timing ................................................................... 496
SCI Input Clock Timing ..................................................................................... 496
Port 4 Block Diagram......................................................................................... 598
Reset during Memory Access (Modes 1 and 2).................................................. 626
Reset during Memory Access (Modes 3 and 4).................................................. 627
0
1
2
7
0
3
4
0
1
2
3
4
5
).......................................................................... 599
).......................................................................... 600
).......................................................................... 601
).......................................................................... 602
).......................................................................... 604
).......................................................................... 606
).......................................................................... 607
).......................................................................... 608
).......................................................................... 609
).......................................................................... 610
).......................................................................... 611
).......................................................................... 612
).......................................................................... 613
4
5
6
7
0
6
1
) ........................................................................ 619
) ........................................................................ 620
) ........................................................................ 621
) ........................................................................ 622
0
1
0
2
4
to P7
and P7
and P8
and PB
and PB
and PA
and PA
to PA
5
).............................................................. 603
7
2
7
) ........................................................... 603
) ........................................................... 605
) ........................................................... 616
2
3
1
3
) ......................................................... 617
) ......................................................... 618
)......................................................... 614
)......................................................... 615